1994 microchip technology inc. ds11109g-page 1 features fast read access time?50 ns cmos technology for low power dissipation - 30 ma active - 100 m a standby fast byte write time?00 m s or 1 ms data retention >200 years high endurance - minimum 100,000 erase/write cycles automatic write operation - internal control timer - auto-clear before write operation - on-chip address and data latches data polling ready/busy chip clear operation enhanced data protection -v cc detector - pulse filter - write inhibit electronic signature for device identi?ation 5-volt-only operation organized 8kx8 jedec standard pinout - 28-pin dual-in-line package - 32-pin plcc package - 28-pin thin small outline package (tsop) 8x20mm - 28-pin very small outline package (vsop) 8x13.4mm available for extended temperature ranges: - commercial: 0?c to +70?c description the microchip technology inc. 28C64A is a cmos 64k non- volatile electrically erasable prom. the 28C64A is accessed like a static ram for the read or write cycles without the need of external components. during a ?yte write? the address and data are latched internally, freeing the micropro- cessor address and data bus for other operations. following the initiation of write cycle, the device will go to a busy state and automatically clear and write the latched data using an internal control timer. to determine when the write cycle is complete, the user has a choice of monitoring the ready/ busy output or using data polling. the ready/busy pin is an open drain output, which allows easy con?uration in wired- or systems. alternatively, data polling allows the user to read the location last written to when the write operation is com- plete. cmos design and processing enables this part to be used in systems where reduced power consumption and reli- ability are required. a complete family of packages is offered to provide the utmost ?xibility in applications package type block diagram a10
ce 21
20
19 v ss
i/o2 14
13
12 oe
a11
a9
a8 22
23
24 rdy/bsy
a12
a7 1
2
3
4
5 25
26
27
28 6
7 nc
we
v cc a6
a5 a4
a3 i/o7
i/o6 i/o5 i/o4
i/o3 i/o1
i/o0
a0
a1 a2 18
17 16
15 11
10
9
8 oe
a11
a9
a8
nc
we
vcc
rdy/bsy
a12
a7
a6
a5
a4
a3 a10
ce
i/07
i/06
i/05
i/04
i/03
vss
i/02
i/01
i/00
a0
a1
a2 1
2
3
4
5
6
7
8
9
10
11
12
13
14 28
27
26
25
24
23
22
21
20
19
18
17
16
15 ?pin 1 indicator on plcc on top of package ?1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15 rdy/bsy
a12
a7
a6
a5
a4
a3
a2
a1
a0
i/o0
i/o1
i/o2
v vcc
we
nc
a8
a9
a11
oe
a10
ce
i/o7
i/o6
i/o5
i/o4
i/o3 ss a6
a5
a4
a3
a2
a1
a0
nc
i/o0 a8
a9
a11
nc
oe
a10
ce
i/o7
i/o6 a7
a12
rdy/bsy
nu
vcc
we
nc i/o1
i/o2
vss
nu
i/o3
i/o4
i/o5 14
15
16
17
18
19
20 4
3
2
1
32
31
30 29
28
27
26
25
24
23
22
21 5
6
7
8
9
10
11
12
13 dip/ soic plcc tsop vsop i/o0 i/o7 input/output
buffers chip enable/
output enable
control logic ce oe data protection
circuitry a12 y gating 16k bit
cell matrix x
decoder y
decoder a0 data
poll auto erase/write
timing v cc v ss we l
a
t
c
h
e
s program voltage
generation rdy/
busy 28C64A 64k (8k x 8) cmos eeprom
28C64A ds11109g-page 2 1994 microchip technology inc. 1.0 electrical characteristics 1.1 maximum ra tings* v cc and input voltages w.r.t. v ss ....... -0.6v to + 6.25v voltage on oe w.r.t. v ss ..................... -0.6v to +13.5v voltage on a9 w.r.t. v ss ...................... -0.6v to +13.5v output voltage w.r.t. v ss .................-0.6v to v cc +0.6v storage temperature ...........................-65?c to +125?c ambient temp. with power applied ........-50?c to +95?c *notice: stresses above those listed under ?aximum ratings may cause permanent damage to the device. this is a stress rat- ing only and functional operation of the device at those or any other conditions above those indicated in the operation listings of this speci?ation is not implied. exposure to maximum rating con- ditions for extended periods may affect device reliability. table 1-1: pin function table name function a0 - a12 address inputs ce chip enable oe output enable we write enable i/o0 - i/o7 data inputs/outputs rdy/busy ready/busy v cc +5v power supply v ss ground nc no connect; no internal connection nu not used; no external connection is allowed table 1-2: read/write operation dc characteristic v cc = +5v 10% commercial (c): tamb = 0?c to +70?c industrial (i): tamb = -40?c to +85?c parameter status symbol min max units conditions input voltages logic ? logic ? v ih v il 2.0 -0.1 vcc+1 0.8 v v input leakage i li -10 10 m av in = -0.1v to vcc +1 input capacitance c in ?0pfv in = 0v; tamb = 25?c; f = 1 mhz (note 2) output voltages logic ? logic ? v oh v ol 2.4 0.45 v v i oh = -400 m a i ol = 2.1 ma output leakage i lo -10 10 m av out = -0.1v to vcc +0.1v output capacitance c out ?2pfv in = 0v; tamb = 25?c; f = 1 mhz (note 2) power supply current, active ttl input i cc 30 ma f = 5 mhz (note 1) v cc = 5.5v power supply current, standby ttl input ttl input cmos input i cc ( s ) ttl i cc ( s ) ttl i cc ( s ) cmos ? 3 100 ma ma m a ce = v ih (0?c to +70?c) ce = v ih (-40?c to +85?c) ce = v cc -0.3 to vcc +1 note 1: ac power supply current above 5mhz: 2ma/mhz. note 2: not 100% tested.
1994 microchip technology inc. ds11109g-page 3 28C64A table 1-3: read operation ac characteristics figure 1-1: read waveforms ac testing waveform: v ih = 2.4v; v il = 0.45v; v oh = 2.0v; v ol = 0.8v output load: 1 ttl load + 100 pf input rise and fall times: 20 ns ambient temperature: commercial (c): tamb = 0?c to +70?c industrial (i): tamb = -40?c to +85?c parameter symbol 28C64A -15 28C64A -20 28C64A -25 units conditions min max min max min max address to output delay t acc 150 200 250 ns oe = ce = v il ce to output delay t ce 150 200 250 ns oe = v il oe to output delay t oe ?0?0 100nsce = v il ce or oe high to output float t off 0 50 0 55 0 70 ns note 1 output hold from address, ce or oe , whichever occurs ?st. t oh 0?? ns note 1 note 1: not 100% tested. address ce v ih v il v ih v il v ih v il oe data we v oh v ol v ih v il address valid high z valid output t acc (1) t off is specified for oe or ce, whichever occurs first (2) oe may be delayed up to t ce - t oe after the falling edge of ce without impact on t ce (3) this parameter is sampled and is not 100% tested high z t oh t off(1,3) notes: t oe(2) t ce(2)
28C64A ds11109g-page 4 1994 microchip technology inc. table 1-4: byte write ac characteristics figure 1-2: programming waveforms ac testing waveform: v ih = 2.4v; v il = 0.45v; v oh = 2.0v; v ol = 0.8v output load: 1 ttl load + 100 pf input rise/fall times: 20 ns ambient temperature: commercial (c): tamb = 0?c to +70?c industrial (i): tamb = -40?c to +85?c parameter symbol min max units remarks address set-up time t as 10 ns address hold time t ah 50 ns data set-up time t ds 50 ns data hold time t dh 10 ns write pulse width t wpl 100 ns note 1 write pulse high time t wph 50 ns oe hold time t oeh 10 ns oe set-up time t oes 10 ns data valid time t dv 1000 ns note 2 time to device busy t db 250ns write cycle time ( 28C64A ) t wc 1 ms 0.5 ms typical write cycle time ( 28C64A f) t wc 200 m s 100 m s typical note 1: a write cycle can be initiated be ce or we going low, whichever occurs last. the data is latched on the pos- itive edge we , whichever occurs ?st. note 2: data must be valid within 1000ns max. after a write cycle is initiated and must be stable at least until t dh after the positive edge of we or ce , whichever occurs ?st. t as t ah t wpl t ds t dh t oes t oeh t wc address ce, we data in oe v ih v il v ih v il v ih v il v ih v il rdy/busy v oh v ol t db t dv busy ready
1994 microchip technology inc. ds11109g-page 5 28C64A figure 1-3: data polling waveforms figure 1-4: chip clear waveforms table 1-5: supplementary control mode ce oe we a9 v cc i/o i chip clear v il v ih v il xv cc extra row read v il v il v ih a9 = v h v cc data out extra row write * v ih * a9 = v h v cc data in note: v h = 12.0v 0.5v. *pulsed per programming waveforms. address valid last written
address valid t acc t ce t wpl t wph t dv t wc t oe true data out data in
valid v ih v il data oe we ce address i/o7 out v ih v il v ih v il v ih v il v ih v il v h v ih ce oe we t s t h t w t s = = 1 s t h = 10ms t w v ih v il v ih v il = 12.0v 0.5v v h
28C64A ds11109g-page 6 1994 microchip technology inc. 2.0 device operation the microchip technology inc. 28C64A has four basic modes of operation?ead, standby, write inhibit, and byte write?s outlined in the following table. 2.1 read mode the 28C64A has two control functions, both of which must be logically satis?d in order to obtain data at the outputs. chip enable (ce ) is the power control and should be used for device selection. output enable (oe ) is the output control and is used to gate data to the output pins independent of device selection. assuming that addresses are stable, address access time (tacc) is equal to the delay from ce to output (tce). data is available at the output t oe after the fall- ing edge of oe , assuming that ce has been low and addresses have been stable for at least t acc -t oe . 2.2 standby mode the 28C64A is placed in the standby mode by applying a high signal to the ce input. when in the standby mode, the outputs are in a high impedance state, inde- pendent of the oe input. 2.3 data protection in order to ensure data integrity, especially during criti- cal power-up and power-down transitions, the following enhanced data protection circuits are incorporated: first, an internal v cc detect (3.3 volts typical) will inhibit the initiation of non-volatile programming operation when v cc is less than the v cc detect circuit trip. second, there is a we ?tering circuit that prevents we pulses of less than 10 ns duration from initiating a write cycle. third, holding we or ce high or oe low, inhibits a write cycle during power-on and power-off (v cc ). operation mode ce oe we i/o rdy/busy (1) read l l h d out h standby h x x high z h write inhibit h x x high z h write inhibit x l x high z h write inhibit x x h high z h byte write l h l d in l byte clear automatic before each ?rite note 1: open drain output. note 2: x = any ttl level. 2.4 w rite mode the 28C64A has a write cycle similar to that of a static ram. the write cycle is completely self-timed and ini- tiated by a low going pulse on the we pin. on the fall- ing edge of we , the address information is latched. on rising edge, the data and the control pins (ce and oe ) are latched. the ready/busy pin goes to a logic low level indicating that the 28C64A is in a write cycle which signals the microprocessor host that the system bus is free for other activity. when ready/busy goes back to a high, the 28C64A has completed writing and is ready to accept another cycle. 2.5 data polling the 28C64A features data polling to signal the comple- tion of a byte write cycle. during a write cycle, an attempted read of the last byte written results in the data complement of i/o7 (i/o0 to i/o6 are indetermin- able). after completion of the write cycle, true data is available. data polling allows a simple read/compare operation to determine the status of the chip eliminat- ing the need for external hardware. 2.6 electronic signature for device identi cation an extra row of 32 bytes of eeprom memory is avail- able to the user for device identi?ation. by raising a9 to 12v 0.5v and using address locations 1feo to 1fff, the additional bytes can be written to or read from in the same manner as the regular memory array. 2.7 chip clear all data may be cleared to 1's in a chip clear cycle by raising oe to 12 volts and bringing the we and ce low. this procedure clears all data, except for the extra row.
1994 microchip technology inc. ds11109g-page 7 28C64A notes
28C64A ds11109g-page 8 1994 microchip technology inc. 28C64A product identi cation system to order or to obtain information, e.g., on pricing or delivery, please use the listed part numbers, and refer to the factory or the listed sales of?es. package: l = plastic leaded chip carrier (plcc) p = plastic dip so = plastic small outline ic ts = thin small outline package (tsop) 8x20mm vs = very small outline package (vsop) 8x13.4mm temperature blank = 0 c to +70 c range: i = -40 c to +85 c access time: 15 150 ns 20 200 ns 25 250 ns shipping: blank tube t tape and reel ??and ?o option: = twc = 1ms f = twc = 200 m s device: 28C64A 8k x 8 cmos eeprom 28C64A f t - 15 i / p americas (continued) san jose microchip technology inc. 2107 north first street, suite 590 san jose, ca 95131 tel: 408 436-7950 fax: 408 436-7955 asia/pacific hong kong microchip technology unit no. 3002-3004, tower 1 metroplaza 223 hing fong road kwai fong, n.t. hong kong tel: 852 2 401 1200 fax: 852 2 401 3431 korea microchip technology 168-1, youngbo bldg. 3 floor samsung-dong, kangnam-ku, seoul, korea tel: 82 2 554 7200 fax: 82 2 558 5934 singapore microchip technology 200 middle road #10-03 prime centre singapore 188980 tel: 65 334 8870 fax: 65 334 8850 taiwan microchip technology 10f-1c 207 tung hua north road taipei, taiwan, roc tel: 886 2 717 7175 fax: 886 2 545 0139 europe united kingdom arizona microchip technology ltd. unit 6, the courtyard meadow bank, furlong road bourne end, buckinghamshire sl8 5aj tel: 44 0 1628 851077 fax: 44 0 1628 850259 france arizona microchip technology sarl 2 rue du buisson aux fraises 91300 massy - france tel: 33 1 69 53 63 20 fax: 33 1 69 30 90 79 germany arizona microchip technology gmbh gustav-heinemann-ring 125 d-81739 muenchen, germany tel: 49 89 627 144 0 fax: 49 89 627 144 44 italy arizona microchip technology srl centro direzionale colleoni palazzo pegaso ingresso no. 2 via paracelso 23, 20041 agrate brianza (mi) italy tel: 39 039 689 9939 fax: 39 039 689 9883 japan microchip technology intl. inc. benex s-1 6f 3-18-20, shin yokohama kohoku-ku, yokohama kanagawa 222 japan tel: 81 45 471 6166 fax: 81 45 471 6122 9/5/95 americas corporate of?e microchip technology inc. 2355 west chandler blvd. chandler, az 85224-6199 tel: 602 786-7200 fax: 602 786-7277 technical support: 602 786-7627 web: http://www.mchip.com/biz/mchip atlanta microchip technology inc. 500 sugar mill road, suite 200b atlanta, ga 30350 tel: 770 640-0034 fax: 770 640-0307 boston microchip technology inc. 5 mount royal avenue marlborough, ma 01752 tel: 508 480-9990 fax: 508 480-8575 chicago microchip technology inc. 333 pierce road, suite 180 itasca, il 60143 tel: 708 285-0071 fax: 708 285-0075 dallas microchip technology inc. 14651 dallas parkway, suite 816 dallas, tx 75240-8809 tel: 214 991-7177 fax: 214 991-8588 dayton microchip technology inc. 35 rockridge road englewood, oh 45322 tel: 513 832-2543 fax: 513 832-2841 los angeles microchip technology inc. 18201 von karman, suite 455 irvine, ca 92715 tel: 714 263-1888 fax: 714 263-1338 new york microchip technology inc. 150 motor parkway, suite 416 hauppauge, ny 11788 tel: 516 273-5305 fax: 516 273-5335 "information contained in this publication regarding device applications and the like is intended through suggestion only and may be superseded by updates. no representation or warranty is given and no liability is assumed by microchip technology incorporated with respect to the accuracy or use of such information, or infringement of patents arising from such use or otherwise. use of microchip's products as critical components in life support systems is not authorized except with express written approval by microchip. no licenses are conveyed, implicitly or otherwise, under any intellectual property rights." the microchip logo and name are registered trademarks of microchip technology inc. all rights reserved. all other trademarks mentioned herein are the property of their respective companies. printed in the usa, 9/95 1995, microchip technology incorporated
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